// +FHDR------------------------------------------------------------
//                 Copyright (c) 2023 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : async_fifo_delay_unit.v
// Author        : ICer
// Created On    : 2023-12-28 17:51
// Last Modified : 2024-01-02 16:59 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module async_fifo_delay_unit #(
    //parameter
    parameter SYNC_CYC = 3,
    parameter WIDTH    = 1
)( /*AUTOARG*/
   // Outputs
   out,
   // Inputs
   clk, rst_n, in
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input clk;
input rst_n;

input [WIDTH -1:0]in;
output[WIDTH -1:0]out;

// ----------------------------------------------------------------
// Wire declare
// ----------------------------------------------------------------

// ----------------------------------------------------------------
// AUTO declare
// ----------------------------------------------------------------
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/

wire [WIDTH -1:0]in_dff[SYNC_CYC :0];
assign in_dff[0] = in;
assign out = in_dff[SYNC_CYC];
 
genvar i;
generate
  for(i=1; i<=SYNC_CYC; i=i+1)begin: inst_rtl
    delay_dffr #(.WIDTH(WIDTH)) u_dffr[i](.clk(clk), .rst_n(rst_n), .d(in_dff[i-1]), .q(in_dff[i]));
  end
endgenerate

endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

